In recent years, devices employing infrared communications means have been used widely. An example of such devices is an infrared communication receiver such as a remote control of home appliances. Generally, to prevent errors in circuits, an infrared communication receiver includes a hysteresis comparator circuit in its output circuit. The hysteresis comparator circuit prevents errors in circuits, such as chattering.
Examples of this infrared communications means include an IrDA (Infrared Data Association) receiving device (infrared receiving device) and an infrared remote control receiving device. Table 1 below shows specifications of the devices, including communication rates, pulse widths, and pulse periods.
TABLE 1COMMUNICATIONPULSERATEWIDTHTIrDA4 Mbps (FIR)(¼) * T500 nsecRECEIVING1.152 Mbps (MIR)(¼) * T868 nsecDEVICE2.4 kbps-115.2( 3/16) * T8.68 usec-kbps (SIR)104 usecINFRARED1 kbps ORDIFFERDIFFERREMOTEBELOWDEPENDINGDEPENDINGCONTROLONONRECEIVINGTRANSMISSIONTRANSMIS-DEVICECODESION CODE
Meanwhile, infrared receiving devices generally have a problem that pulse widths fluctuate, depending on receiving distances. It depends on receiving distances whether or not the specifications for the pulse widths are satisfied. When the specifications are not satisfied, communication errors occur. Therefore, there have been demands for an infrared receiver that includes a hysteresis comparator circuit so as to maintain conventional capability of preventing errors, and at the same time, to allow output-pulse widths to be stable.
In recent years, an increasing number of multimedia devices such as wireless keyboards have been including an infrared remote control system utilizing transmission codes of short periods and short pulse widths to speed up transmission and to drive at low power-consumption. This gives rise to increasing demands for development of infrared receivers capable of receiving the transmission codes of short periods and short pulse widths.
Hysteresis comparator circuits responsive to such demands are disclosed in, for example, Japanese Utility Model Application Publication No. 132127/1989 (Jitsukaihei 1-132127) (published on Sep. 7, 1989) and Japanese Unexamined Patent Publication No. 152509/2003 (published on May 23, 2003). The following describes, as a conventional circuit, a comparing circuit 2000 employing the hysteresis comparator circuit disclosed in the publications above, with reference to FIGS. 23 to 25.
FIG. 23 is a circuit diagram showing an exemplary configuration of the comparing circuit 2000 employing a conventional hysteresis comparator circuit. FIG. 24 is a circuit diagram showing an exemplary and concrete configuration of a hysteresis comparator circuit 2200 in the comparing circuit 2000. FIG. 25 shows waveforms in operations of the comparing circuit 2000.
As shown in FIG. 23, the comparing circuit 2000 includes: a charging and discharging circuit 2100 to charge and discharge a capacitor 2109 (capacitance Cx); the hysteresis comparator circuit 2200; an output circuit 2300; an input section 2001 via which a signal is supplied to the charging and discharging circuit 2100; and an output section 2002 via which an output signal of the output circuit 2300 is output.
In the figures, “MN” indicates an N-channel MOSFET, and “MP” indicates a P-channel MOSFET. When a voltage equal to or higher than a threshold voltage (Vth) is applied across a gate and a source, conduction is made between a drain and the source, and current flows. Hereinafter, the voltage applied across the gate and the source will be abbreviated as Vgs. Further, “ON” indicates that conduction is made between the drain and the source, and “OFF” indicates that conduction is made between the drain and the source.
The following describes basic operations, and configuration, of the charging and discharging circuit 2100, with reference to FIGS. 23 and 25.
In the charging and discharging circuit 2100, when a pulse signal, i.e. an input voltage (Vin), is fed into the input section 2001, a voltage Vgs lower than the threshold voltage is applied to the MN2105 if Vin=Low. Therefore, the MN2105 becomes MN2105=OFF. Thus, the constant-current Iy supplied from the current source 2108 is mirrored by the current mirror formed by the MN2106 and the MN2107, and is drawn from the capacitor 2109, whereby the capacitor 2109 is discharged.
At this time, the MP2101 becomes MP2101=ON. Therefore, the constant-current Ix supplied from the current source 2104 flows through a path from the Vcc to the GND via the MP2101. Thus, no current flows through the MP2102 and the MP2103. Accordingly, when Vin=Low, the capacitor 2109 is discharged.
When Vin=High, the MP2101 becomes MP2101=OFF, and the MN2105 becomes MN2105=ON. When MP2101=OFF, the constant-current Ix is mirrored by the current mirror formed by the MP2102 and the MP2103, and flows through the capacitor 2109, whereby the capacitor 2109 is charged. Further, when the MN2105 is MN2105=ON, the constant-current Iy flows through a path from the Vcc to the GND via the MN2105. Thus, no current flows through the MN2106 and the MN2107. Accordingly, when Vin=High, the capacitor 2109 is charged.
A capacitor voltage (Csig_x), which indicates a voltage of the capacitor 2109, changes according to whether Vin=High or Vin=Low. In other words, the capacitor voltage Csig_x changes according to whether it is charging or discharging.
As shown in FIG. 25, at point A where Vin=High, charging the capacitor 2109 starts. Thus, the capacitor voltage Csig_x rises. From point A to point C, the capacitor voltage Csig_x rises at a fixed time constant. At point C where the capacitor voltage Csig_x rises to Vcc, charging reaches saturation, and the capacitor voltage Csig_x is fixed. At point D where Vin=Low, discharging the capacitor 2109 starts. Thus, the capacitor voltage Csig_x drops. From point D to point F, the capacitor voltage Csig_x drops at a fixed time constant. At point F where the capacitor voltage Csig_x drops to GND (0V), discharging completes, and the capacitor voltage Csig_x is fixed.
The following describes basic operations, and configurations, of the hysteresis comparator circuit 2200 and the output circuit 2300, with reference to FIGS. 23 to 25. The output circuit 2300 is connected to an output end of the hysteresis comparator circuit 2200
As shown in FIG. 23, the hysteresis comparator circuit 2200 includes a comparator circuit section 2201 and a reference power-source 2202. The reference power-source 2202 generates a hysteresis threshold voltage (Vth_his) has a hysteresis characteristic. The hysteresis comparator circuit 2200 compares the capacitor voltage Csig_x of the charging and discharging circuit 2100 with the hysteresis threshold voltage Vth_his.
Specifically, as shown in FIG. 24, the hysteresis comparator circuit 2200 receives the capacitor voltage Csig_x as an input voltage (+in), and outputs an output current (Iout) responsive to a result of comparison of the capacitor voltage Csig_x with the hysteresis threshold voltage Vth_his. At this time, the value of the hysteresis threshold voltage Vth_his changes on the basis of the result of comparison. This is discussed in the following description.
(i) Case in Which +in<Vth_His
The constant-current Iw supplied from the current source 2220 flows through the MN2211, is mirrored by the current mirror formed by the MP2213 and the MP2214, and flows through the resistor 2217 (resistance Ry) and the resistor 2216 (resistance Rx). Accordingly, the hysteresis threshold voltage Vth_his is expressed by Equation (1) below
                                                        Vth_his              =              Vth_H                                                                          =                                                Rx                  ×                  Iv                                +                                                      (                                          Rx                      +                      Ry                                        )                                    ×                  Iw                                                                                        Equation        ⁢                                  ⁢                  (          1          )                    where, “H” in “Vth_H” indicates High.At this time, no current flows through the MN2212. Thus, Iout=0.(ii) Case in Which +in>Vth_His
The constant-current Iw supplied from the current source 2220 flows through the MN2212. Thus, a voltage drop of Rz×Iw occurs in the R2218 (resistance Rz). Therefore, a voltage equal to or higher than the threshold voltage is applied across the gate and the source of the MP2215. As a result, the MP2215 becomes ON, and the output current Iout is output. At this time, no current flows through the MN2211. Accordingly, the hysteresis threshold voltage Vth_his is expressed by Equation (2) below
                                                        Vth_his              =              Vth_L                                                                          =                              Rx                ×                Iv                                                                        Equation        ⁢                                  ⁢                  (          2          )                    
(where “L” in “Vth_L” indicates Low).
Accordingly, from cases (i) and (ii) above, the hysteresis voltage range is
                                                        Vhis              =                              Vth_H                -                Vth_L                                                                                        =                                                (                                      Rx                    +                    Ry                                    )                                ×                                  Iw                  .                                                                                        Equation        ⁢                                  ⁢                  (          3          )                    
In the output circuit 2300, in case (i) above, Iout=0, and the MN2301 and the MN2302 become OFF. Therefore, the output voltage (Vout) becomes High (=Vcc). In case (ii) above, on the other hand, the output current Iout flows, and the MN2301 and the MN2302 become ON. Therefore, the output voltage Vout becomes Low (=GND).
The following describes fluctuations in the output voltage Vout when Vin=High and when Vin=Low, with reference to FIG. 25.
As shown in FIG. 25, Csig_x<Vth_his when the capacitor voltage Csig_x is at point A. Therefore, the hysteresis threshold voltage Vth_his becomes Vth_H. Thus, Vout=High. When charged to point B, the capacitor voltage Csig_x becomes Csig_x>Vth_H. Therefore, the hysteresis threshold voltage Vth_his drops to Vth_L. Thus, Vout=Low. When discharged to point E, the capacitor voltage Csig_x becomes Csig_x<Vth_his. Therefore, the hysteresis threshold voltage Vth_his rises to Vth_H. Thus, the output voltage Vout becomes Vout=High.
In FIG. 25, the pulse width is indicated as pw, a delay time in a response from the time when the input voltage Vin rises to High to the time when the output voltage Vout drops to Low is indicated as t1, a delay time in a response from the time when the input voltage Vin drops to Low to the time when the output voltage Vout rises to High is indicated as t2, and a period from the time when the input voltage Vin drops to Low and to the time when the capacitor voltage Csig_x is discharged completely to Low is indicated as t3. The capacitor 2109 is charged by the constant-current Ix shown in FIG. 23, and discharged by the constant-current Iy also shown in FIG. 23. The times t1 to t3 are expressed by Equations (4) to (6) below, respectively
                                                                        t                ⁢                                                                  ⁢                1                            =                              Cx                ×                                                      (                                          Vth_H                      -                      0                                        )                                    /                  Ix                                                                                                        =                              Cx                ×                                  Vth_H                  /                  Ix                                                                                        Equation        ⁢                                  ⁢                  (          4          )                                                  t          ⁢                                          ⁢          2                =                  Cx          ×                                    (                              Vcc                -                Vth_L                            )                        /            Iy                                              Equation        ⁢                                  ⁢                  (          5          )                                                                                            t                ⁢                                                                  ⁢                3                            =                              Cx                ×                                                      (                                          Vcc                      -                      0                                        )                                    /                  Iy                                                                                                        =                              Cx                ×                                  Vcc                  /                                      Iy                    .                                                                                                          Equation        ⁢                                  ⁢                  (          6          )                    
The following describes countermeasures against errors such as chattering in the comparing circuit 2000, with reference to FIG. 26. FIG. 26 shows waveforms in operations of the comparing circuit 2000 at the time when errors occur.
As shown in FIG. 26, the capacitor voltage Csig_x discharges at a time constant t/V=Cx/Iy even when a pulse of the input pulse Vin splits (y in the figure) due to noise or the like. Thus, the capacitor voltage Csig_x does not become the hysteresis threshold voltage Vth_his or lower rapidly. Further, the hysteresis voltage range Vhis of Equation (3) is given to the hysteresis threshold voltage Vth_his so that the output voltage Vout is less likely to be involved with errors.
In the comparing circuit 2000, however, the capacitor voltage Csig_x discharges at the time constant t/V=Cx/Iy to prevent errors such as chattering. Therefore, a period of time (t3) for the capacitor voltage Csig_x to be discharged completely from the High-level to the Low-level is long. Thus, there is a problem that a period (T) of a first pulse of the output voltage Vout becomes short if a period (Toff) in which the pulse of the input voltage Vin is Low is shorter than the time t3. This is discussed in the following description, with reference to FIG. 27.
FIG. 27(a) shows waveforms in operations of the comparing circuit 2000 at the time when Toff>t3. FIG. 27(b) shows waveforms in operations of the comparing circuit 2000 at the time when Toff<t3. In the figures, “T” indicates a pulse period, “Ton” indicates a period in which the pulse is High, and “Toff” indicates a period in which the pulse is Low (pause period). The input voltage Vin having a pulse of a period T (Ton+Toff) is fed continuously from time t=0.
As shown in FIG. 27(a), when Toff>t3, the capacitor voltage Csig_x discharges completely to Low before a second pulse is fed. Thus, the period of the output voltage Vout is normal.
As shown in FIG. 27(b), when Toff<t3, a second pulse of the input voltage Vin is fed before the capacitor voltage Csig_x discharges completely. Thus, the charging period of the second pulse of the capacitor voltage Csig_x becomes shorter by a time-period from a to b in the figure. Specifically, the period for the second pulse of the output voltage Vout to drop to Low becomes shorter by the time-period from a to b, compared to the case of FIG. 27(a) in which Toff>t3 and there is no overlap in the capacitor voltage Csig_x. As a result, there arises a problem that the period of the first pulse of the output voltage Vout becomes shorter than the pulse period of the input voltage Vin.
This problem is solved if the discharging period of the capacitor voltage Csig_x is set short. Specifically, the problem is solved if the discharging period with respect to the pulse of the input voltage Vin shown in FIG. 27(b) is set in such a way as to satisfy t3x<Toff<t3 (t3x indicates t3 of the case in which the discharging period is shortened) to avoid an overlap in the waveform of the capacitor voltage Csig_x. However, if the discharging period is shortened, the capability of preventing errors, such as chattering, shown in FIG. 26 is degraded. Accordingly, there is a problem that the capability of outputting a pulse having a same period as that of an input pulse having a short pause period and the capability of preventing errors are in trade-off relationship.